The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology may now permit single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second, to be packaged in relatively small semiconductor device packages. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memories; the circuitry used to store digital information. Conventional random access memory devices may include a variety of circuits, such as SRAM and DRAM circuits. SRAMs are mainly used in applications that require a high random access speed. DRAMs, on the other hand, are mainly used for high-density applications where the slow random access speed of DRAM can be tolerated.
Some SRAM cell designs may be based on NDR (Negative Differential Resistance) devices. They usually consist of at least two active elements, including an NDR device. The NDR device is important to the overall performance of this type of SRAM cell. A variety of NDR devices have been introduced ranging from a simple bipolar transistor to complicated quantum-effect devices. One advantage of the NDR-based cell is the potential of having a cell area smaller than conventional SRAM cells (e.g., either 4T or 6T cells). Many of the typical NDR-based SRAM cells, however, have not been widely adopted in commercial SRAM products because of certain limitations including, e.g., high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for the cell operation; sensitivity to manufacturing variations; poor noise-margins; limitations in switching speeds; limitations in operability due to temperature, noise, voltage and/or light stability; and associated manufacturability and yield issues which may be due to processes variations in fabrication and the like.
One type of NDR-based memory, a thyristor-based memory, has been recently introduced to potentially provide the speed of conventional SRAM at the density of DRAM in a CMOS compatible process. More specifically, a thin capacitively-coupled thyristor (“TCCT”) type device may serve as a bi-stable element in memory applications. For more general details of such thyristor-based memory, reference may be made to: “A Novel High Density, Low Voltage SRAM Cell With A Vertical NDR Device,” VLSI Technology Technical Digest, June, 1998; “A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-Scale Memories,” International Electron Device Meeting Technical Digest 1999, and “A Semiconductor Capacitively-Coupled NDR Device And Its Applications For High-Speed High-Density Memories And Power Switches,” PCT Int'l Publication No. WO 99/63598, corresponding to U.S. patent application Ser. No. 09/092,449, now U.S. Pat. No. 6,229,161. Each of these documents is incorporated by reference in its entirety.
An important design consideration in any type of thyristor-based memory cell, including the TCCT memory cell, is the holding current of the thyristor. The holding current of the thyristor may refer to the minimum current required to preserve the thyristor's forward conducting state.
Another important consideration when using a thyristor-based memory cell may be its sensitivity to environmental factors that may cause error when it is in the blocking state. A thyristor may be vulnerable to error responsive to various adverse environmental conditions such as noise, light, anode-to-cathode voltage changes and high temperatures. Such vulnerability can affect the operation of the thyristor and result in undesirable turn-on, which in turn could disrupt the contents of the memory cell. Accordingly, there may be a compromise in the desire to reduce its vulnerability to adverse conditions and the desire to achieve low holding current.
During manufacture of a thyristor-based memory, various doping, implant, activation and anneal procedures may be performed. Some of these procedures may also be dependent on masking as may be used during patterning for the doping and implant provisions, as well as for patterning for other structures, such as polysilicon for the electrodes. These various procedures—e.g., patterning, masking, doping, implanting, siliciding annealing, etc.—during fabrication of the thyristor memory may, therefore, be understood to contribute to its overall manufacturing complexity, cost and size. The tolerances available for each of these procedures and the limitations in reproducibility therefor may further be understood to impact product reliability and yields.